Silicon oxide dielectric layers form resilient interfaces with silicon and provide high dielectric strength and a relatively low dielectric constant. These traits result in heavy use of silicon oxide for insulating electrically active features from one another. Two conventional methods for depositing a silicon oxide layer include: (1) oxidation process wherein silicon is oxidized at relatively high temperatures (e.g., sometimes more than 1000° C.); and (2) a chemical vapor deposition (CVD) process wherein the silicon and oxygen sources are introduced into a chamber and exposed to energy (e.g., heat) to form a silicon oxide layer. Silicon oxide CVD processes typically occur at temperatures ranging from 600° C. to 800° C. or below 450° C. depending on the application. While satisfactory for larger integrated circuit linewidths, these methods can cause diffusion at interfaces due to the high deposition temperature, thereby degrading electrical characteristics of miniature electrical devices.
In addition to lower substrate temperatures, thin layers used in semiconductor devices will increasingly require atomic layer control during deposition due to the decreasing linewidths. These thin layers will also be required to have excellent step coverage. Silicon precursors have been interleaved with oxygen precursors to deposit silicon oxide, but predominantly at high substrate temperatures or by including a halogen in the precursors.
Methods are needed to broaden the process space in which silicon oxide may be deposited with atomic layer control.